The present invention relates to a timing calibration method for an IC tester for testing ICs such as memories and an IC tester equipped with a calibration function using the calibration method.
FIG. 11 depicts the general outlines of a commonly known IC tester. Reference character TES designates generally the IC tester. The IC tester TES comprises a main controller 111, a pattern generator 112, a timing generator 113, a waveform formatter 114, a logic comparator 115, a driver group 116, a comparator group 117, a failure analysis memory 118, a logical amplitude reference voltage source 121, a comparison reference voltage source 122 and a device power supply 123.
The main controller 111 is formed, in general, by a computer system and operates under the control of a test program prepared by a user, controlling the pattern generator 112 and the timing generator 113. The pattern generator 112 generates test pattern data, which is converted by the waveform formatter 114 to a test pattern signal that has an actual waveform, and the test pattern signal is provided to and stored in an IC under test 119 after being voltage-amplified by the driver group 116 to a waveform having an amplitude value set in the logical amplitude reference voltage source 121.
For example, when the IC under test 119 is an IC memory, a response signal read out of the IC under test 119 is compared by the comparator group 117 with a reference voltage from the comparison reference voltage source 122 to decide the logic level (voltage of a logic xe2x80x9cHxe2x80x9d, voltage of a logic xe2x80x9cLxe2x80x9d) of the response signal. The logic level thus decided is compared by the logic comparator 115 with an expected value that is output from the pattern generator 112; if a mismatch is found between the logic level and the expected value, it is decided that the memory cell of the address from which the response signal was read out is failing, and upon each occurrence of such a failure, the faulty address is stored in the failure analysis memory 118 for use in deciding, after completion of the test, whether the failed cell is repairable.
The timing generator 113 generates timing that defines the rise and fall timing of the waveform of the test pattern signal that is applied to the IC under test 119, and the timing of a strobe pulse that defines the timing for logical comparison by the logic comparator 115.
The respective timing is described in the user""s prepared program so that at the user""s intended timing the IC under test 119 can be actuated and tested for normal operation.
A description will be given, with reference to FIG. 12, the general outlines of the timing generator 113 and the waveform formatter 114. FIG. 12 depicts the general configurations of the waveform formatter and the timing generator for generating a one-channel test pattern signal. The waveform formatter 114 can be formed by an S-R flip-flop, which is supplied at its set and reset terminals S and R with set and reset pulses PS and PR, respectively, to generate a test pattern signal TS that rises at predetermined timing T1 and falls at predetermined timing T2. In FIG. 12 the outputs from clock generators 113A and 113B are shown to be provided directly to the S-R flip-flop for the sake of brevity, but in practice, the connection of the outputs from a plurality of clock generators to the S-R flip-flop is controlled in real time in accordance with the waveform mode and pattern data.
The set and reset pulses PS and PR are generated by the pair of clock generators 113A and 113B. The generation timing of the set and reset pulses PS and PR by the clock generators 113A and 113B is defined by pieces of delay data DYS and DYR available from a delay data memory 113C.
The delay data memory 113C is accessed with an address signal that is provided from an address counter 113D. The address counter 113D generates an address signal whose address is incremented by one for each test cycle TSRAT after the start of testing; based on the address signal, an address assignment is made for each test cycle TSRAT during the test period, then delay data preset for each test cycle TSRAT is read out, and the read-out delay data is set in the clock generators 113A and 113B, which generate the set pulse PS and the reset pulse PR in accordance with the delay data.
FIGS. 13A-13E show how the above operations are carried out. The set pulse PS is generated at timing delayed, by given delay data DYS1, behind, for instance, the rise timing of a rate clock RAT that defines the test cycle TSRAT, and generates the reset pulse PR at timing delayed behind the rise timing of the rate clock RAT by delay data DYR1, thereby generating the test pattern signal TP of a pulse width corresponding to the time difference TPW between the set and reset pulses PS and PR (see FIG. 13E). The resolution for setting the set and reset pulses PS and PR is defined by the pulse interval of a clock CK depicted in FIG. 13B.
From the above it will be understood that the test pattern signal TP can be set to rise and fall at arbitrary timing within the test cycle TSRAT.
Next, the operation of the comparator group 117 will be described. The comparator group 117 performs:
(a) an operation of deciding the logic of the response signal from the IC under test 119 by comparing it with a predetermined reference level at predetermined timing and capturing the decided logical value; and
(b) an operation of measuring the timing of the rise or fall of the response output signal TX.
FIGS. 14A-14F are explanatory of the operation (a). In the case of the operation (a), the comparator sets the timing of a strobe pulse STB at the timing when the response output signal TX ought to arrive, and captures the logical value of the response output signal TX at the set timing of the strobe pulse STB. In the FIG. 14 example, since the strobe pulse STB is set in the H-logic period of the response output signal TX, the comparator captures the H logic that is the result of the logic decision as shown in FIG 14D. Accordingly, when the expected value in this test cycle is H as depicted in FIG. 14, the result of the logical comparison by the logic comparator 115 is decided to be OK (good) as shown in FIG 14F.
FIGS. 15A-15E are explanatory of the operation (b). In the case of measuring the timing of the rise and fall of the response output signal TX, the phase of the strobe pulse STB that is applied to the comparator 17 is shifted for each test cycle TSRAT within the range of the test cycle TSRAT or within the range several times longer than the test cycle, the logical value of the comparator output varies at the timing of the strobe pulse, and the rise timing and fall timing of the response output signal are decided based on the timing of the strobe pulse at the time the state of the logical decision output reverses as depicted in FIG. 14D.
From the description given above with reference to FIGS. 11 to 15, it will be understood that the conventional IC tester has the capabilities of arbitrarily setting the generation timing of the test pattern signal and measuring the timing of the rise and fall of the response output signal TX from the IC under test.
The IC tester performs a timing calibration for in-phase application of test pattern signals to respective pins of the IC under test and a timing calibration for in-phase reading of response output signals from the IC under test into the IC tester.
A conventional method of timing calibration adopts a scheme that adjusts the delay times of variable delay circuits inserted in signal paths of respective pins to provide the same delay time on the signal paths.
The following two schemes are used to measure the delay time of the signal path.
(1) The time of reflection of the signal propagating along the signal path is measured through utilization of the timing measuring capability of the IC tester and the propagation delay time of the signal path is computed from the measured time of reflection.
(2) A probe is held in touch with each pin of an IC socket on which the IC under test is mounted, then a calibration pulse applied to each pin of the IC socket is applied via the probe to an oscilloscope to measure the phase difference between the calibration pulse and a signal of a reference phase, and the propagation delay time of each signal path is calculated from the phase difference.
With the scheme (1), the reflected wave of the calibration pulse is poor in waveform quality. This inevitably decreases the accuracy in detecting the arrival of the reflected wave, resulting in the accuracy of timing calibration being low.
With the scheme (2), since the oscilloscope is used to measure the phase difference between the signal under measurement and the reference signal, the measurement accuracy is high. Hence, the timing calibration can be performed with high accuracy.
With the measuring scheme (2), however, the signal path that permits calibration is limited specifically to a signal path equipped with a driver capable of sending a signal to the IC socket, and the signal path with only the comparator is not subject to measurement by this method. Hence, the signal path with only the comparator requires measuring its propagation delay time through utilization of the reflected wave as mentioned above in (1). Accordingly, the measuring scheme (2) is high in the accuracy of the timing calibration for the driver-associated path but low in the calibration accuracy for the comparator-associated path, and hence it has the defect of decreased accuracy in timing calibration as a whole.
Furthermore, the scheme (2) involves the preparation of an oscilloscope that is not ever necessary for IC testing. A two-input oscilloscope is expensive which has a configuration that outputs data corresponding to the phase difference between two signals and sends the data to the IC tester to adjust the delay time of a variable delay circuit. Thus, this method requires the preparation of such a costly oscilloscope only for timing calibration, and hence it is economically disadvantageous.
An object of the present invention is to provide a timing calibration method for an IC tester that reduces the cost for timing calibration and permits accurate timing calibration irrespective of the driver- or comparator-associated path, and an IC tester that possesses the function of implementing the timing calibration method.
The present invention implements a timing calibration through utilization of the afore-mentioned timing generation and timing measurement features which common IC testers have inherently.
According to a first aspect of the present invention, there is provided a timing calibration method for an IC tester which uses a probe with a reference comparator, said method comprising the steps of:
(a) selectively contacting respective pins of an IC socket one after another by said probe from outside;
(b) applying a calibration pulse from a driver of said IC tester to each pin of said IC socket;
(c) capturing said calibration pulse applied from said driver to said each pin by said reference comparator of said probe at the timing of a reference strobe pulse that is provided to said reference comparator;
(d) calculating a deviation between the timing of said calibration pulse and the timing of said reference strobe pulse; and
(e) adjusting the delay time of a variable delay circuit provided in each signal path of said driver so that said deviation takes a predetermined value.
According to a second aspect of the present invention, there is provided a timing calibration method which uses a probe with a reference driver, said method comprises the steps of:
(a) selectively contacting respective pins of an IC socket one after another by said probe from outside;
(b) applying a reference calibration pulse from said reference driver to each pin of said IC socket;
(c) capturing said reference calibration pulse applied from said reference driver to each pin by each comparator of said IC tester at the timing of a strobe pulse that is provided to said each comparator;
(d) calculating a deviation between the timing of said reference calibration pulse and the timing of said strobe pulse; and
(e) adjusting the delay time of a timing calibrating variable delay circuit inserted in a signal path of said strobe pulse so that said deviation takes a predetermined value.
According to a third aspect of the present invention, there is provided IC tester equipped with a calibration function which has drivers each provided in correspondence with one of pins of an IC socket on which ICs under test are placed, for applying a test pattern signal to the input terminal of each IC under test, and a comparator for capturing the logical value of a response output signal provided at the output terminal of each IC under test, and decides whether the response signal captured by said comparator coincides with a predetermined expected value to test said IC under test for normal operation, said IC tester comprising:
a probe for selectively contacting the pins of said IC socket one after another;
a reference comparator mounted in said probe, for capturing a signal applied to the pin of said IC socket contacted by said probe at the timing of a reference strobe pulse;
a driver variable delay circuit provided in the signal path of each of said drivers, for adjusting the delay time of the signal to be provided to the pin of said IC socket;
a strobe variable delay circuit provided in the signal path of the strobe pulse to be provided to said each driver, for adjusting the delay time of said strobe pulse; and
calibration control means for comparing the logical value of the signal captured by said reference comparator with an expected value and for controlling said driver variable delay circuit so that the phase of a calibration pulse applied to the pin of said IC socket from said each driver coincides with reference timing of said reference strobe pulse.
According to the present invention, since it is decided whether the timing of the calibration pulse captured from the IC socket into the probe coincides with reference timing through utilization of a timing measuring function that the IC tester inherently possesses, any particular expensive jig, such as an oscilloscope, need not be provided outside the tester. Hence, the timing calibration can be performed at low cost.
Further, according to the present invention, the reference driver is mounted in the probe and the calibration pulse of a reference phase is applied from the reference driver to the pin of the IC socket with which the probe is in contact. The calibration pulse is captured by the comparator of the IC tester via a cable or the like from the pin of the IC socket.
The comparator of the IC tester measures the timing of the calibration pulse while sequentially shifting the phase of the strobe pulse. Based on the timing measured result, the delay time of a variable delay circuit inserted in the signal path of the strobe pulse is set so that the timing of, for example, the leading edge of the calibration pulse coincides with reference timing, with which the timing calibration of the comparator is completed.
As described above, the present invention utilizes the timing measuring capability of the IC tester to perform timing calibration, and hence does not require any particular jig. This provides an advantage that the cost for timing calibration is very low.
Moreover, the present invention utilizes a direct wave as a signal for measuring the propagation delay time of the signal path, and hence the invention provides highly accurate measurement results. This also leads to highly accurate timing calibration.
Besides, according to the present invention, the probe is mounted on an automatic positioning device (robot), by which the probe is automatically brought into contact with each pin of the IC socket. This produces the advantage of automated timing calibration as well.
Furthermore, since the present invention offer a timing calibration device that has a plurality of probes and simultaneously performs timing calibration of driver- and comparator-associated signal paths connected to a plurality of IC sockets, it is also possible to sharply reduce the time for calibration.